A time/space switch LSI with a 300-Mb/s CMOS low-power I/O interface

Author

Yokomizo, Koichi ; Morikawa, Koichi ; Itakura, Tadayuki ; Haga, Kazukiyo ; Morimoto, Kunio ; Tabata, Hirosuke

Author_Institution

VLSI R&D Center, Oki Electr. Ind. Co. Ltd., Tokyo, Japan

fYear

1995

fDate

1-4 May 1995

Firstpage

443

Lastpage

446

Abstract

This paper introduces a 156 Mb/s×6 time/space switch LSI for SDH cross-connect systems. To minimize I/O power consumption, we implemented a low-power differential CMOS I/O circuit which can apply to up to 622-Mb/s data transmission. The chip was designed by using a silicon compilation tool and fabricated using 0.5-μm CMOS process technology. Functions up to 300-Mb/s I/O operation and 0.9-W total power consumption have been confirmed. This chip uses a 208-pin plastic QFP with a multi layer lead structure

Keywords

CMOS digital integrated circuits; broadband networks; large scale integration; synchronous digital hierarchy; telecommunication switching; 0.5 micron; 0.9 W; 300 Mbit/s; CMOS low-power I/O interface; CMOS process technology; I/O power consumption; SDH cross-connect systems; differential I/O circuit; multi layer lead structure; plastic QFP; silicon compilation tool; time/space switch LSI; total power consumption; CMOS process; CMOS technology; Circuits; Data communication; Energy consumption; Large scale integration; Plastics; Silicon; Switches; Synchronous digital hierarchy;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518220

Filename

518220