A new hierarchical algorithm for transistor placement in CMOS macro cell design

We present a new transistor placement algorithm for generating a uni-height macro cell layout. The algorithm first partitions the transistors constituting a cell into clusters, and provides a set of alternative transistor placements in a cluster for each cluster. And then both selection from each set and placement of clusters are performed simultaneously, by iterative improvement method. This simultaneous improvement method enables one to get a good solution in practical time. Experimental results on our gate-array cell library shows that the resultant placements are comparable to manual placements done by skilled layout designers, in terms of width and intra-cell routing congestion