Title :
Concurrent logic and layout design system for high performance LSIs
Author :
Murakata, M. ; Murofushi, M. ; Igarashi, M. ; Aoki, T. ; Ishioka, T. ; Mitsuhashi, T. ; Goto, N.
Author_Institution :
ULSI Res. Labs., Toshiba Corp., Kawasaki, Japan
Abstract :
This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration
Keywords :
concurrent engineering; integrated circuit layout; integrated logic circuits; large scale integration; logic design; 100 MHz; concurrent system; high performance LSIs; interconnection delays; layout design; logic design; Capacitance; Delay estimation; Design methodology; Design optimization; Integrated circuit interconnections; Large scale integration; Logic design; Power system interconnection; Timing; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518225
