A 90.7 MHz-2.5 million transistors CMOS CPLD with JTAG boundary scan and in-system programmability

Author

Patel, Rakesh ; Wong, Myron ; Costello, John ; Reese, Dirk ; Bocchino, Vincent ; Chu, Michael ; Turner, John

Author_Institution

ALTERA Corp., San Jose, CA, USA

fYear

1995

fDate

1-4 May 1995

Firstpage

507

Lastpage

510

Abstract

This paper discusses a complex programmable logic device which provides up to 12,000 usable gates. The EPM9560 is the first member of the third-generation MAX 9000 family. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 560 product term based macrocells and circuit techniques to achieve an overall 90.7 MHz system operating frequency. The device is designed to operate in a 3.3 V or 5 V systems. It has built-in JTAG boundary scan for improving testability and in-system programmability for ease of manufacturing

Keywords

CMOS logic circuits; boundary scan testing; programmable logic arrays; 3.3 V; 5 V; 90.7 MHz; CMOS CPLD; EPM9560; MAX 9000; built-in JTAG boundary scan testability; complex programmable logic device; in-system programmability; logic array block; macrocells; multi-dimensional interconnects; CMOS logic circuits; Circuit testing; Frequency; Integrated circuit interconnections; Logic arrays; Logic circuits; Logic devices; Macrocell networks; Programmable logic arrays; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518234

Filename

518234