Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

Author

Roullard, J. ; Farcy, A. ; Capraro, S. ; Lacrevaz, T. ; Bermond, C. ; Houzet, G. ; Charbonnier, J. ; Fuchs, C. ; Ferrandon, C. ; Leduc, P. ; Flechet, B.

Author_Institution

IMEP-LAHC, Univ. de Savoie, Le Bourget du Lac, France

fYear

2012

fDate

May 29 2012-June 1 2012

Firstpage

8

Lastpage

13

Abstract

3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.

Keywords

ball grid arrays; integrated circuit interconnections; logic circuits; microprocessor chips; three-dimensional integrated circuits; 3D interconnect routing; 3D stacking technology; TSV density; back 3D stacking; high speed data transmission; high speed signal transmission; interposer technology; logic applications; memory-processor; processor-BGA channels; Bandwidth; Delay; Face; Frequency measurement; Integrated circuit interconnections; Stacking; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

978-1-4673-1966-9

Electronic_ISBN

0569-5503

Type

conf

DOI

10.1109/ECTC.2012.6248798

Filename

6248798