Title :
A 0.75-V, 0.7 MHz CMOS 32-bit RISC microprocessor for portable applications
Author :
Suzuki, Hiroaki ; Sakai, Toshiichika ; Harigai, Hisao ; Yano, Yoichi
Author_Institution :
ULSI Syst. Dev. Lab., NEC Corp., Kawasaki, Japan
Abstract :
A 32-bit RISC microprocessor “V810” that has 5-stage pipeline structure and a 1 K byte, direct-mapped instruction cache realizes 0.7 MHz operation at 0.75 V, dissipating 330 μW power consumption. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by 0.8 μm double metal-layer CMOS process technology to integrate 240,000 transistors on 7.4 mm×7.1 mm die
Keywords :
CMOS digital integrated circuits; microprocessor chips; reduced instruction set computing; 0.7 MHz; 0.75 V; 0.8 micron; 32 bit; 330 muW; RISC microprocessor; V810; direct-mapped instruction cache; double metal-layer CMOS technology; noise margin; pipeline structure; portable applications; power consumption; pseudo-static circuit; rail-to-rail swing; CMOS logic circuits; CMOS process; Circuit synthesis; Clocks; Energy consumption; Laboratories; Low voltage; Microprocessors; Pipelines; Reduced instruction set computing;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518249
