DocumentCode
2720981
Title
An 800 MHz 1-micron CMOS pipelined 8-bit adder using true single-phase logic-flip-flops
Author
Rogenmoser, Robert ; Huang, Qiuting
Author_Institution
Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
fYear
1995
fDate
1-4 May 1995
Firstpage
581
Lastpage
584
Abstract
An 8-bit adder, operating at 800 MHz, and a single-stage bit-serial adder, running at more than 1 GHz, have been implemented and successfully tested in a standard 1.0 μm CMOS process. The performance was achieved through the use of carry-increment full adders, fine-grain pipelining, and merging the combinational logic into the pipeline registers
Keywords
CMOS logic circuits; adders; flip-flops; pipeline arithmetic; 1 micron; 8 bit; 8-bit adder; 800 MHz; CMOS process; carry-increment full adders; combinational logic; fine-grain pipelining; pipeline registers; single-phase logic-flip-flops; single-stage bit-serial adder; Adders; CMOS logic circuits; CMOS process; CMOS technology; Delay; Flip-flops; Logic circuits; Pipeline processing; Registers; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-2584-2
Type
conf
DOI
10.1109/CICC.1995.518251
Filename
518251
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