• DocumentCode
    2720993
  • Title

    A 64 bit carry look-ahead CMOS adder using Modified Carry Select

  • Author

    Morinaka, Hiroyuki ; Makino, Hiroshi ; Nakase, Yasunobu ; Suzuki, Hiroaki ; Mashiko, Koichiro

  • Author_Institution
    Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
  • fYear
    1995
  • fDate
    1-4 May 1995
  • Firstpage
    585
  • Lastpage
    588
  • Abstract
    We present a 64 b Carry Look-ahead (CLA) adder having a 2.6 ns delay time at 3.3 V power supply within 0.27 mm2 using a 0.5 μm CMOS technology. We derived its structure from considering the tradeoffs between speed and area. This consideration includes not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. Moreover we introduced a new carry select scheme called Modified Carry Select (MCS). MCS has 20% area advantage over the conventional Carry Select Adder (CSA)
  • Keywords
    CMOS logic circuits; adders; 0.5 micron; 2.6 ns; 3.3 V; 64 bit; Modified Carry Select; carry look-ahead CMOS adder; gate capacitance delay; gate intrinsic delay; wiring delay; Adders; CMOS technology; Capacitance; Delay effects; Laboratories; Large scale integration; Microprocessors; Voltage; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
  • Conference_Location
    Santa Clara, CA
  • Print_ISBN
    0-7803-2584-2
  • Type

    conf

  • DOI
    10.1109/CICC.1995.518252
  • Filename
    518252
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2720993