Leading-zero anticipatory logic for high-speed floating point addition

Author

Suzuki, Hiroaki ; Nakase, Yasunobu ; Makino, Hiroshi ; Morinaka, Hiroyuki ; Mashiko, Koichiro

Author_Institution

Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1995

fDate

1-4 May 1995

Firstpage

589

Lastpage

592

Abstract

This paper describes new Leading-Zero Anticipatory (LZA) Logic for high-speed floating-point addition (FADD). This method carries out the pre-decoding for the normalization concurrently with the addition for significand. Besides, it performs the shift operation in parallel with the rounding operation. The proposed logic consists of the simple circuit with 1.8% penalty in transistor count. The FADD core using the proposed logic operates at 160 MHz, where the core has been fabricated with 0.5 μm CMOS technology with triple metal interconnections

Keywords

CMOS logic circuits; adders; application specific integrated circuits; floating point arithmetic; 0.5 micron; 160 MHz; ASICs; CMOS technology; FADD; high-speed floating point addition; leading-zero anticipatory logic; predecoding; rounding operation; shift operation; triple metal interconnections; Adders; CMOS logic circuits; CMOS technology; Delay effects; Integrated circuit interconnections; Inverters; Laboratories; Large scale integration; Logic circuits; Logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518253

Filename

518253