A bit-level scalable median filter using simple majority circuit

A median filtering algorithm based on binary radix is presented. It performs mask-and-set operations and takes the majority at each binary digit. The majority bits thus constitute the median value in the set of binary numbers. A circuit composed of output-wired inverters is used to implement the majority function. Through a buffering inverter, the majority bit comes out in just two inverter delays. A simple design, less hardware and thus faster speed can be achieved. A bit-level scalable median filter architecture using this algorithm is proposed. It works in a pipelined style, is useful in real-time image smoothing, and is suitable for VLSI implementation