DocumentCode
2721096
Title
A verification technique for communication hardware and its application to a real chip design
Author
Fujita, Masahiro ; Chen, Bing ; Yamazaki, Masami
Author_Institution
Fujitsu Lab. of America Inc., San Jose, CA, USA
fYear
1995
fDate
1-4 May 1995
Firstpage
619
Lastpage
622
Abstract
We present an abstraction technique for formal hardware verification by which we can verify realistic site chips for communication systems. The abstraction method makes it possible to abstract away datapaths relating to the packets format of communicating data. We successfully applied it to verification of the buffer control operations in one of our communication chips in parallel to the design process
Keywords
circuit CAD; formal verification; integrated circuit design; telecommunication equipment; abstraction technique; buffer control operations; chip design; communication chips; communication hardware; formal hardware verification; verification technique; Application specific integrated circuits; Chip scale packaging; Communication system control; Formal verification; Hardware; Process design; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-2584-2
Type
conf
DOI
10.1109/CICC.1995.518259
Filename
518259
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