Title :
Speeding up power estimation by topological analysis
Author :
Cheng, D.I. ; Marek-Sadowska, M. ; Kwang-Ting Cheng
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
We present an efficient technique to speedup the power estimation process for combinational circuits. Our approach is based on a topological analysis of the underlying circuit using the concept of supergates. We also present an optimal algorithm for calculating the supergate structures. In addition to speeding up, we also point out that certain nodes in a given circuit are more crucial than other nodes to be estimated accurately. Experimental results are very encouraging.
Keywords :
CMOS logic circuits; combinational circuits; estimation theory; network topology; probability; switching theory; BDD-based techniques; combinational circuits; optimal algorithm; power estimation; process speedup; supergate structures; topological analysis; Binary decision diagrams; Boolean functions; Circuit simulation; Circuit testing; Clocks; Combinational circuits; Data structures; Integrated circuit modeling; Probability; Switching circuits;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518260
