Title :
Mixed-mode timing simulation for accurate CMOS bridging fault detection
Author :
Tian, Yanmei ; Hajj, Ibrahim N.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
A bridging fault simulator of CMOS VLSI circuits with timing information is described. It can detect delay as well as logic faults. A realistic resistive two-line bridging fault model is used. Mixed-mode bridging fault simulation without timing information is performed first to detect those faults that cause logic errors so as to reduce the fault set. Test vector selection, and mixed-mode timing simulation techniques are then used to speed up the simulation. Simulation results of some of the ISCAS 89 sequential benchmark circuits are given
Keywords :
CMOS logic circuits; VLSI; circuit analysis computing; delays; fault diagnosis; fault location; logic testing; timing; CMOS VLSI circuits; CMOS bridging fault detection; bridging fault simulator; delay detection; logic fault detection; mixed-mode timing simulation; resistive two-line bridging fault model; test vector selection; timing information; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Delay; Electrical fault detection; Fault detection; Semiconductor device modeling; Timing; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518263
