Arithmetic built-in self-test for digital signal processing architectures

Author

Adham, S. ; Kassab, M. ; Mukherjee, N. ; Radecka, E. ; Rajski, J. ; Tyszer, J.

Author_Institution

MACS Lab., McGill Univ., Montreal, Que., Canada

fYear

1995

fDate

1-4 May 1995

Firstpage

659

Lastpage

662

Abstract

In this paper, we present a new non-intrusive built-in self test (BIST) methodology, aimed at improving testability of DSP architectures. The method utilizes the arithmetic blocks in DSP data paths to perform test pattern generation and test response compaction. Consequently, it requires virtually no area overhead and results in no performance degradation. Furthermore, it can be used for at-speed testing thereby providing a capability to detect failures that may not be detectable by conventional low speed testing

Keywords

built-in self test; digital arithmetic; digital signal processing chips; integrated circuit testing; logic testing; DSP architectures; DSP data paths; arithmetic BIST; arithmetic blocks; at-speed testing; built-in self test; digital signal processing architectures; test pattern generation; test response compaction; testability improvement; Automatic testing; Circuit testing; Compaction; Degradation; Digital arithmetic; Digital signal processing; Electronic equipment testing; Integrated circuit testing; Logic testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518267

Filename

518267