Title :
Extensible and Configurable Processors for System-on-Chip Design
Author :
Nurmi, J. ; Leibson, S. ; Campi, F. ; Panis, C.
Author_Institution :
Tampere Univ. of Technol.
Abstract :
Extensible, configurable, and reconfigurable processor cores mark the start of a new epoch for microprocessors, more suited to SoC design. In this chapter, we present four approaches to achieve higher levels of application-specific performance. Acceleration of a baseline RISC core with a reconfigurable co-processor can provide high performance with a very small amount of configuration data. VLIW DSP approach supporting efficient compiler technology provides a straightforward path for design space exploration and implementation from high-level language entry. An extensible RISC core provides application performance by incorporating new instruction into the instruction set, and finally, a run-time reconfigurable RISC core integrates the application-specific logic into the processor pipeline as a reconfigurable picoGA array
Keywords :
coprocessors; digital signal processing chips; high level languages; instruction sets; multiprocessing systems; parallel architectures; pipeline processing; program compilers; reconfigurable architectures; reduced instruction set computing; system-on-chip; RISC core; SoC; VLIW DSP approach; application-specific logic; compiler technology; digital signal processor; high-level language; instruction set; microprocessor; picoGA array; pipeline processor; reconfigurable coprocessor; reduced instruction set computing; system-on-chip design; very long instruction word; Acceleration; Coprocessors; Digital signal processing; Logic arrays; Microprocessors; Process design; Reduced instruction set computing; Space technology; System-on-a-chip; VLIW;
Conference_Titel :
Advanced Signal Processing, Circuits, and System Design Techniques for Communications, 2006
Conference_Location :
Kos
Print_ISBN :
1-4244-0460-6
DOI :
10.1109/ASPCAS.2006.251123