Electrical characterization method to study barrier integrity in 3D through-silicon vias

Author

Li, Y.-L. ; Velenis, D. ; Kauerauf, T. ; Stucchi, M. ; Civale, Y. ; Redolfi, A. ; Croes, K.

Author_Institution

IMEC, Leuven, Belgium

fYear

2012

fDate

May 29 2012-June 1 2012

Firstpage

304

Lastpage

308

Abstract

In this paper, the controlled I-V (IV_ctrl) method is adopted for the barrier integrity characterization of TSVs at wafer level. Planar capacitor structures are used for the initial validation of the IV_ctrl method with respect to the traditional time dependent dielectric breakdown (TDDB) methodology. The TDDB field acceleration factor of the TSV liner is extracted by IV_ctrl in a reasonable time, and the results demonstrate that defective barriers can degrade TDDB field acceleration factor and thus TSV liner reliability.

Keywords

electric breakdown; integrated circuit reliability; three-dimensional integrated circuits; 3D through-silicon vias; I-V method; IV_ctrl method; Planar capacitor structures; TDDB field acceleration factor; barrier integrity characterization; electrical characterization method; traditional time dependent dielectric breakdown methodology; Acceleration; Breakdown voltage; Dielectrics; Reliability; Stress; Through-silicon vias; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

978-1-4673-1966-9

Electronic_ISBN

0569-5503

Type

conf

DOI

10.1109/ECTC.2012.6248846

Filename

6248846