• DocumentCode
    2721794
  • Title

    Chip on Board development for a novel MEMS accelerometer for seismic imaging

  • Author

    Zhang, Zhuqing ; Wu, Jennifer ; Bernard, Sheldon ; Walmsley, Robert G.

  • Author_Institution
    Technol. Dev. Organ., Hewlett Packard Co., Corvallis, OR, USA
  • fYear
    2012
  • fDate
    May 29 2012-June 1 2012
  • Firstpage
    350
  • Lastpage
    355
  • Abstract
    HP is developing a MEMS accelerometer that offers high sensitivity and low noise level for seismic application. During the packaging process, it was found that the thermal mechanical stress resulted from the CTE mismatch between the silicon and the substrate can distort the MEMS structure and alter the device performance. A finite element model was established to understand the effect of substrate material, die attach material and package geometry on the scale factor and bias offset of the MEMS. The model predicted that ceramic substrate introduced less variation of the sensor performance over the operating temperature range (-40 to 70°C) than the FR4 substrate. In order to use the low cost FR4 substrate, one can use die attach adhesive with low modulus and/or small die attach area to minimize the gap and displacement. Ceramic packages and Chip on Board (COB) packages on FR4 substrate were built using various die attach adhesives to validate the model. The performance of the MEMS was measured from -40 to 70°C. Results showed that using a low modulus adhesive with full coverage and moderate thickness provides minimum temperature distortion. On the other hand, a high modulus adhesive can be employed if the die attach area is reduced. The model also indicated that by modifying the structure of the substrate, the stress on MEMS can be reduced. MEMS on pillar packages were built and evaluated to confirm the modeling result.
  • Keywords
    accelerometers; ceramic packaging; chip-on-board packaging; finite element analysis; microsensors; CTE mismatch; FR4 substrate; MEMS accelerometer; MEMS structure; bias offset; ceramic packages; ceramic substrate; chip on board development; chip on board packages; device performance; die attach adhesive; die attach area; die attach material; finite element model; low noise level; package geometry; packaging process; pillar packages; scale factor; seismic application; seismic imaging; sensor performance; substrate material; temperature -40 C to 70 C; temperature distortion; thermal mechanical stress; Ceramics; Microassembly; Micromechanical devices; Silicon; Stress; Substrates; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
  • Conference_Location
    San Diego, CA
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4673-1966-9
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2012.6248854
  • Filename
    6248854