DocumentCode
2721931
Title
Challenges for process and product integration at 45nm
Author
Stork, H.
Author_Institution
Texas Instruments Inc., Dallas, TX
fYear
2006
fDate
24-26 April 2006
Abstract
Abstract form only given. To fully realize the benefits of CMOS scaling, new process generations must reach high yield at low cost, rapidly. Product design faces both higher complexity of process integration, including geometrical effects like strain engineering, as well as a larger need to accurately predict many systematic and random variations. These design-for-manufacturing challenges force an unprecedented interaction of physical design and process optimization for the first generation of 45nm CMOS systems
Keywords
CMOS integrated circuits; design for manufacture; integrated circuit yield; product design; 45 nm; CMOS scaling; design for manufacturing; geometrical effects; physical design; process integration; process optimization; product design; strain engineering; CMOS process; Capacitive sensors; Costs; Design engineering; Design optimization; Instruments; Process design; Product design; USA Councils;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2006 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
1-4244-0181-4
Type
conf
DOI
10.1109/VTSA.2006.251112
Filename
4016585
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