VDD Scaling for FinFET Logic and Memory Circuits: the Impact of Process Variations and SRAM Stability

As CMOS technology is fast moving towards the scaling limit, the FinFET is considered as the most promising structure down to 22nm node (Frank et al., 1992; Huang et al., 1999). Both FinFET-based logic and SRAM have been demonstrated recently (Rainey et al., 2002; Nowak et al.,2002). However, with scaling of the device dimensions, process-induced variations cause an increasing spread in the distribution of circuit delay and power, and affecting the robustness of VLSI designs (Burnett et al., 1994). SRAM has become the focus of technology scaling since embedded SRAM is estimated to occupy nearly 90% of the chip area in the near future (2003). Due to the area-constrained limit, the device fluctuation in the SRAM cell is significant. In this paper, we explore the performance of FinFET technology in digital circuit applications at 90 nm technology node under various device parameter variations. Comprehensive comparison of FinFET vis-a-vis PD-SOI has been done for logic gates as well as memory structures that are most commonly used in commercial VLSI designs. We also compare the performance of these two technologies at ultra-low voltages for future low-power applications