Title :
Mixed Pitch BGA (mpBGA) packaging development for high bandwidth-high speed networking devices
Author :
Savic, John ; Nagar, Mohan ; Xie, Weidong ; Ahmad, Mudasir ; Senk, David ; Bansal, Anurag ; Islam, Nokibul ; Oh, Park Gun ; Pendse, Raj ; HangChul, Choi ; SangHo, Lee
fDate :
May 29 2012-June 1 2012
Abstract :
High speed network packaging solutions have pushed the limits of known manufacturing technology into previously untested realms. Next generation ASIC´s and SiP/MCM´s are requiring packages in excess of 60mm × 60mm. These large package sizes present both significant manufacturability and reliability challenges. Developing new solutions which can adequately accommodate the needs of high speed interconnect while concurrently mitigating package size growth and the consequential reliability and manufacturability risks which result, is essential for maintaining a supply equilibrium at a sustainable cost. This paper discusses the manufacturing process and the component reliability of a large body size (55×55mm) ASIC package TV using 40nm ELK Si technology and a Mixed Pitch Ball Grid Array (mpBGA) with BGA-side capacitance on both thin core (0.4mm) and 8+1 coreless substrates. Suitable for use at any body size, mpBGA combines tighter BGA pitch (0.94mm) and the option for BGA-side capacitance to enable optimal package decoupling and increased interconnect density. mpBGA provides a means for mitigating package size growth by inherently extending the usefulness of smaller package sizes, thereby minimizing both the package reliability risks as well as the cost associated with proving in the “next” body size up (i.e increasing from 55×55mm to 60×60mm packages). The preferred method for assembly and design of mpBGA packages on both coreless and thin core substrates will be discussed including: (1) assembly process capability, (2) preferred board level design stack-up and (3) preferred package design footprint incorporating the BGA-side capacitors. A preferred BOM has been identified for the thin-core 55×55mm package which has resulted in full-pass of all relevant L1 reliability tests (MSL-4 preconditioning, HTS, uHAST and 1000TCB). Additionally, it is shown that the package co-planarity of the 55×55mm thin-core te- t vehicle is within the required 8 mil maximum for large body size flip chip BGA packages.
Keywords :
application specific integrated circuits; assembling; ball grid arrays; capacitors; elemental semiconductors; fine-pitch technology; flip-chip devices; integrated circuit interconnections; integrated circuit manufacture; integrated circuit packaging; integrated circuit reliability; silicon; system-in-package; 1000TCB; 8+1 coreless substrates; BGA-side capacitance; BGA-side capacitors; BOM package; ELK silicon technology; HTS; L1 reliability tests; MCM; MSL-4 preconditioning; Si; SiP; assembly method; bill of materials; consequential reliability; high bandwidth-high speed networking devices; high speed interconnection; high speed network packaging; interconnect density; large body size ASIC package test vehicle; large body size flip chip BGA packages; manufacturability risks; manufacturing process; manufacturing technology; mixed pitch BGA packaging; mixed pitch ball grid array; mpBGA packaging design; next generation ASIC; optimal package decoupling; package reliability risks; package size growth mitigation; preferred board level design stack-up; preferred package design footprint; size 0.4 mm; size 40 nm; system-in package; thin core substrates; thin-core test vehicle; uHAST; Assembly; Capacitors; Qualifications; Reliability; Silicon; Substrates;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6248870