• DocumentCode
    2722057
  • Title

    A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications

  • Author

    Kelkar, Ram ; Flye, Dave ; Malladi, Anjali ; Natonio, Joseph ; Scoville, Chris ; Short, Ken ; Thiagarajan, Pradeep

  • Author_Institution
    IBM Microelectron. Div., Essex Junction, VT
  • fYear
    2005
  • fDate
    19-23 Sept. 2005
  • Firstpage
    7
  • Lastpage
    10
  • Abstract
    This paper describes a wide-range programmable frequency synthesizer building block for 4.25Gbps serial link applications. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as damping in order to minimize output jitter. The synthesizer architecture includes pre and post dividers to maximize programmability. A novel implementation of the high speed divide circuit is also described
  • Keywords
    frequency synthesizers; high-speed integrated circuits; jitter; programmable circuits; 4.25 Gbit/s; high speed divide circuit; loop gain; low jitter programmable frequency synthesizer; serial link applications; variable gain charge pumps; Bandwidth; Charge pumps; Clocks; Damping; Frequency synthesizers; Gain; Jitter; Microelectronics; Phase locked loops; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference, 2005. Proceedings. IEEE International
  • Conference_Location
    Herndon, VA
  • Print_ISBN
    0-7803-9264-7
  • Type

    conf

  • DOI
    10.1109/SOCC.2005.1554443
  • Filename
    1554443
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2722057