An IR drop-driven placer for standard cells in a SOC design

A partition-based IR drop-driven algorithm is proposed for standard cell placement. Different cost functions for reducing IR drop are used in the horizontal cut and vertical cut partitioning processes. In addition to minimizing the total wire length, we balance the power consumption of the two partitions during the horizontal cut partitioning process. During the vertical cut partitioning process, we move the cells with higher power consumption closer to the power sources to reduce the maximum IR drop of the row. After placement is finished, we apply a greedy placement refinement process to further reduce the value of the maximum IR drop. Each standard cell row is modeled with an equivalent conductance model. Then the IR drop of each row is calculated and analyzed. We compare the placement generated by the proposed approach with the wire length-driven placement. On average, the proposed approach improves the value of maximum IR drop by 51%. Therefore, it reduces the need to add power straps on the chip and more routing resources are saved