Combined simulator statistics and block code sampling to study performance enhancement of microarchitecture

Author

Shi, Huibin ; Bailey, Chris ; Farrall, Glenn ; Hastie, N. ; Jenkins, Sam

Author_Institution

Dept. of Comput. Sci., York Univ., UK

fYear

2005

fDate

25-28 Sept. 2005

Firstpage

33

Lastpage

36

Abstract

This paper presents a simple approach combining the statistics of simulation and block code sampling to study the performance enhancement of the microarchitecture with duplicated pipelines (enhanced microarchitectures). We collect the statistics from the simulation of EEMBC benchmark code on a TriCore™ 2.0 implementation and use them to sample blocks of code and simulate different enhanced microarchitectures. The new simulation results are used to analyse the performance benefits of each microarchitecture enhancement, which can narrow down the design space exploration.

Keywords

circuit simulation; integrated circuit design; microprocessor chips; EEMBC benchmark code; TriCore 2.0; block code sampling; duplicated pipelines; microarchitecture performance enhancement; simulator statistics; Analytical models; Assembly; Block codes; Fluid flow measurement; Frequency; Microarchitecture; Microprocessors; Performance analysis; Sampling methods; Statistics;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2005. Proceedings. IEEE International

Print_ISBN

0-7803-9264-7

Type

conf

DOI

10.1109/SOCC.2005.1554449

Filename

1554449