A Flow Graph Technique for DFT Controller Modification

This paper presents a novel DFT method which requires very small modification to a controller in RT-level description of a circuit. The control/data flow graph (CDFG) representation of an RTL circuit is used for analyzing the testability of individual RT-level operations within a hierarchical test technique. Using a non-scan arrangement, existing data paths are utilized to provide controllability and observability to RT-level operations. Furthermore, additional data paths are introduced by altering the controller states or signals. Post behavioral synthesis information and pre-computed test vectors of the individual modules are utilized. This method considerably reduces the test application time by ignoring unnecessary control states in the test process