Challenges and improvements for 3D-IC integration using ultra thin (25μm) devices

The semiconductor industry has followed the Moore´s Law for more than 40 years. The concept of scaling based on this law is now approaching the end and to maintain the same scaling concept new routes are being investigated. These new routes are commonly identified as `More-than-Moore´ technologies and the most important of them is 3D-IC integration. By 3D-IC Integration it is possible to put more transistors on the same footprint without the need to shrink transistor sizes. However, as for any new technology, there are many challenges and issues that need to be addressed before moving to high volume manufacturing [1]. In this work we present the challenges and required improvements identified for 3D stacking in case of ultra thin devices with TSVs (Thru Silicon Vias). In particular, the challenges related to wafer thinning, flip chip bumping, 3D stacking and packaging.