A low jitter delay-locked loop with a realignment duty cycle corrector

Author

Li, Luoqing ; Hou-Ming Chen, J. ; Chen-Hao Chang, R.

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung

fYear

2005

fDate

19-23 Sept. 2005

Firstpage

73

Lastpage

76

Abstract

In this paper, a new delay-locked loop (DLL) architecture is proposed to effectively improve the DLL jitter performance. A novel realignment duty cycle corrector (RDCC) is proposed for the DLL. The RDCC circuit can make the output waveform of the DLL maintain a 50% duty cycle in a lock mode. The RDCC circuit has advantages of low power consumption, small chip area and high operating frequency. The proposed DLL adopts the clean ref-clock signal and the locked signal to do the "realignment" operation, which improves the jitter performance. The DLL is designed using the TSMC 0.35mum 2P4M CMOS technology. HSPICE simulation results show that the proposed DLL jitter is effectively reduced 61% at 250MHz with a 3.3V supply

Keywords

CMOS integrated circuits; SPICE; circuit simulation; delay lock loops; integrated circuit testing; jitter; 0.35 micron; 250 MHz; 2P4M CMOS technology; 3.3 V; DLL jitter performance; HSPICE simulation; clean ref-clock signal; delay-locked loop architecture; locked signal; realignment duty cycle corrector; realignment operation; Delay; Instruments; Jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2005. Proceedings. IEEE International

Conference_Location

Herndon, VA

Print_ISBN

0-7803-9264-7

Type

conf

DOI

10.1109/SOCC.2005.1554458

Filename

1554458