Title :
Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP
Author :
Zhan, Chau-Jie ; Tzeng, Pei-Jer ; Lau, John H. ; Dai, Ming-Ji ; Chien, Heng-Chieh ; Lee, Ching-Kuan ; Wu, Shang-Tsai ; Kao, Kuo-Shu ; Huang, Shin-Yi ; Fan, Chia-Wen ; Chung, Su-Ching ; Huang, Yu-Wei ; Lin, Yu-Min ; Chang, Jing-Yao ; Yang, Tsung-Fu ; Chen,
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
fDate :
May 29 2012-June 1 2012
Abstract :
In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.
Keywords :
copper; integrated circuit design; integrated circuit modelling; integrated circuit reliability; stacking; system-in-package; three-dimensional integrated circuits; 3D IC; Cu; SiP; TSV/RDL/IPD interposer; assembly process; embedded stress sensors; multi-chip-stacking; non-destructive inspection; reliability assessments; system-in-package; thermal modeling; through-silicon-via; Semiconductor device measurement; Silicon; Stacking; Substrates; Temperature measurement; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6248883
