DocumentCode
2722359
Title
High current-carrying and highly-reliable 30μm diameter Cu-Cu area-array interconnections without solder
Author
Khan, Sadia A. ; Kumbhat, Nitesh ; Goyal, Abhishek ; Okoshi, Kodai ; Raj, Pulugurtha ; Meyer-Berg, Georg ; Sundaram, Venky ; Tummala, Rao
Author_Institution
3D Syst. Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2012
fDate
May 29 2012-June 1 2012
Firstpage
577
Lastpage
582
Abstract
Innovative packaging technologies have delivered a remarkable generation of mobile devices, enabling the transition from simple single-function systems to advanced multifunctional computing and communication systems in the span of only a decade. Of many technology advancements, high interconnection (I/O) density has been a major contributing factor in this transition. However, the constant push for high I/O density has resulted in smaller pitch and interconnection dimensions, thereby introducing the concerns for thermo-mechanical reliability and electromigration resistance due to higher current density. Georgia Tech Packaging Research Center (GT-PRC) has been developing an ultra-fine pitch, copper-to-copper interconnection technology to overcome the limitations of current solder bump technology. This paper emphasizes the robustness of this interconnection technology by demonstrating its performance under high current density and high I/O area-array configuration. Already demonstrated at 30μm pitch, low profile copper-to-copper interconnections, developed at GT-PRC using a low-cost, low-temperature direct copper-to-copper bonding approach, have been shown [1-2] to have high reliability under thermal cycling test (TCT), high temperature storage (HTS) test and highly accelerated stress test (HAST). Utilized in the pioneering chip-last approach, this interconnection method has also been proven [3] ready for commercialization through a two-step high throughput multi-chip embedding process and three-dimensional stacking capability. This research demonstrates, for the first time, the ability of the aforementioned adhesive-bonded copper-to-copper interconnections to - (1) withstand 2000 thermal cycles in a high pin-count area-array configuration and (2) survive ~800 hours of testing at 104-105 A/cm2 current density, which, to the best of authors´ knowledge is the highest ever reported for adhesive based interconnections [4-6].
Keywords
adhesive bonding; copper; integrated circuit bonding; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; life testing; adhesive based interconnections; chip last approach; copper-to-copper interconnection technology; high current carrying interconnections; high temperature storage test; highly accelerated stress test; highly reliable area-array interconnections; packaging technology; size 30 mum; thermal cycling test; ultrafine pitch interconnection technology; Copper; Current density; Electromigration; Flip chip; Reliability; Resistance; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4673-1966-9
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2012.6248888
Filename
6248888
Link To Document