Constraint-based Code mapping for heterogeneous Chip multiprocessors

Mapping a real-time embedded application onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an ILP (integer linear programming) based framework that maps a given application (represented as a task graph) onto an HCM (heterogeneous chip multiprocessor) architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use dynamic voltage scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility