Architecture and design methodology for synthesizable reconfigurable array targeting wireless system-on-chip applications

This paper presents a novel domain specific reconfigurable architecture and an associate design methodology for system-on-chip (SoC) platform which provides flexibility as well as low-power consumption. Two Viterbi decoders, which are widely used in wireless communication system, are implemented on the proposed architecture using the proposed design methodology. The measured performance shows that our architecture is a perfect compromise between the ASICs and generic FPGAs, and hence suitable for future portable mobile devices