Metrology and inspection rquirements for 3D stacking of ICs

As semiconductor devices become smaller and smaller, to keep up with Moore´s law, their manufacturing cost increases. Transistors have been continuing to scale and improve in performance. However, the performance improvement gained by scaling is gradually becoming insignificant compared to the negative effects of the interconnect scaling. This had been already predicted by Bohr et al. in 1995. One of the workable ways forward is by reducing the average length of the interconnects. This can be done by forming a new type of vertical interconnect technology that achieves micron scale connections known as TSVs. In order to make this new technology a success several metrology and inspection requirements need to be tackled. In general, the critical 3D processes have been identified to be (i) TSV formation (ii) IC wafer thinning (iii) Debonding and stacking module. In the table below the key challenges within each of the modules have been identified and also the possible solutions for each one of the challenges have been mentioned.