DocumentCode :
2722452
Title :
Impact of Back Gate Bias on Hot-Carrier Effects of n-channel Tri-Gate FETs (TGFETs)
Author :
Lin, Chia-Pin ; Tsui, Eing-Yue
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., National Chiao Tung Univ., Hsinchu
fYear :
2006
fDate :
24-26 April 2006
Firstpage :
1
Lastpage :
2
Abstract :
The hot-carrier effects of non-planar tri-gate SOI FET (TGFET) with back-gate bias were investigated. Negative back gate bias could raise the influence of buried oxide defects and then degrade the device quickly. For TGFETs with ultra-narrow fin width and side gate extension, the smaller buried oxide interface area and more obvious screening effect terminate the field lines to obviate the back gate bias efficiently. The extrapolated hot-carrier lifetime encourages the TGFETs as promising sub-10nm devices
Keywords :
carrier lifetime; field effect transistors; hot carriers; silicon-on-insulator; 10 nm; SOI; back gate bias; hot carrier effects; n-channel; oxide interface area; tri gate FET; CMOS process; CMOS technology; Degradation; Electron traps; FETs; Hot carrier effects; Hot carriers; Human computer interaction; Stress; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems, and Applications, 2006 International Symposium on
Conference_Location :
Hsinchu
ISSN :
1524-766X
Print_ISBN :
1-4244-0181-4
Electronic_ISBN :
1524-766X
Type :
conf
DOI :
10.1109/VTSA.2006.251076
Filename :
4016612
Link To Document :
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