Title :
A novel five-transistor (5T) sram cell for high performance cache
Author :
Wieckowski, Michael ; Margala, Martin
Author_Institution :
Rochester Univ., NY
Abstract :
A novel five-transistor (5T) static memory cell is presented for applications in high-speed, low-power cache. The 5T design in 0.18mum bulk CMOS exhibits 57% faster operation speed, a 12% reduction in power, and a 6% reduction in area with respect to the standard 6T cell design
Keywords :
CMOS integrated circuits; SRAM chips; cache storage; 0.18 micron; CMOS integrated circuit; five transistor SRAM cell; high speed cache; static memory cell; Capacitance; Digital signal processors; Fabrication; Integrated circuit interconnections; Inverters; Microcontrollers; Power system interconnection; Random access memory; Voltage; Writing;
Conference_Titel :
SOC Conference, 2005. Proceedings. IEEE International
Conference_Location :
Herndon, VA
Print_ISBN :
0-7803-9264-7
DOI :
10.1109/SOCC.2005.1554469
