Process development for high-current electrochemical deposition of copper pillar bumps

In electrochemical deposition (ECD) of copper for either through silicon via (TSV) or copper pillar bumps (CPB), a high plating current density is often desirable to speed up the copper fill-up, or deposition rate, hence increasing the process throughput and lowering the overall fabrication cost. A set of optimized ECD parameters for high-speed copper deposition to form pillar bumps, however, must take into considerations both the yield and quality of the resulting bump growth across the entire wafer. In this paper, we discuss some bump deposition results found when attempts were made to speed up the ECD deposition rate using high current densities and high bath temperature within the recommended ranges. It was found that the materials used - the plating bath solutions, thick photoresists, strip chemicals, and the ECD plating conditions such as temperature, current, and even soak time, all play interactive roles. A clearly visible abnormality, in the form of a skin coating around the sidewalls of the plated copper posts was found when a combination of high temperature (>;40°C) and high current densities (above 30ASD) was used for ECD plating. To reduce and eliminate such aberrations, more moderate plating conditions were applied and shown to be effective. Possible causes for the chemical formation of this sidewall coating and the optimal ranges of plating parameters for the high-speed copper plating baths studied here are presented at the conclusion.