Challenge of design and test of ultra-large-scale circuits

Summary form only given. It is pointed out that, with the advent of ultra-large-scale integration, the design and test of digital circuits are becoming more and more difficult. Effective approaches to solving this problem are hierarchical processing and structured design-for-testability. It is noted that design verification and automatic test generation systems can handle a circuit with millions of gates by using a hierarchical processing approach and a partitioning technique based on scan-path structure