A Low Power Heterogenous Reconfigurable Architecture For Embedded Generic Finite State Machines

Author

Liu, Zhenyu ; Khawam, Sami ; Arslan, Tughrul ; Erdogan, Ahmet T.

Author_Institution

Sch. of Eng. & Electron., Edinburgh Univ.

fYear

2005

fDate

19-23 Sept. 2005

Firstpage

113

Lastpage

114

Abstract

Domain-specific reconfigurable arrays are usually designed for specific applications and provide a good compromise between speed, power and flexibility. In this paper, a novel reconfigurable finite state machine (FSM) array is presented for implementing generic FSMs. Compared with commercial FPGA devices, the new architecture provides the following reductions: up to 90% in power consumption, up to 55% in area and around 20% in delay time

Keywords

embedded systems; finite state machines; low-power electronics; reconfigurable architectures; system-on-chip; FPGA devices; domain specific reconfigurable arrays; finite state machine array; generic FSM; heterogenous reconfigurable architecture; power consumption; Automata; Boolean functions; Computer architecture; Costs; Design engineering; Energy consumption; Reconfigurable architectures; Reconfigurable logic; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2005. Proceedings. IEEE International

Conference_Location

Herndon, VA

Print_ISBN

0-7803-9264-7

Type

conf

DOI

10.1109/SOCC.2005.1554474

Filename

1554474

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2722557