Author :
Chung, C.H. ; Chien, T. ; Hsiao, J.S. ; Chu, C.H. ; Kuo, W.S. ; Cheng, C.C. ; Li, F. ; Nieh, S. ; Wu, S. ; Wang, B. ; Wang, C. ; Hu, T. ; Hsiao, G. ; Che, M. ; Hon, R.Y. ; Chen, H.M. ; Chou, G. ; Chang, G. ; Chou, L. ; Shu, H.C. ; Huang, K.Y. ; Tsai, V.
Abstract :
A new DRAM cell design for 70nm generation is demonstrated. We develop a novel cell design which is different from that previously published for trench DRAM technology and can be shrunk into 70nm generation. Some innovative processes are also introduced to successfully demonstrated the cell function
Keywords :
DRAM chips; integrated circuit design; isolation technology; nanotechnology; 70 nm; DRAM cell design; cell transistor; checker board pattern design; deep trench isolation; Capacitance; Costs; Dry etching; Filling; Grain size; Investments; Isolation technology; Process design; Random access memory; Space technology;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2006 International Symposium on
