Title :
Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing
Author :
Joshi, Akanksha ; Davis, J.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
Abstract :
Because of the continuous increase in transistor count, interconnect complexity, and operating frequencies of system-on-chip (SoC) designs, power and area have become critical issues. Power, noise, and area reduction of soft intellectual property (IP) cores using a low-overhead wave-pipelined multiplexed (WPM) interconnect routing technique is proposed. Using system-level simulation, it is shown that the application of WPM routing decreases power by 14% and core area by 28% for a core area-centric design, and for a wire coupling-centric design, power reduces by 6% and wire coupling by 20%
Keywords :
integrated circuit design; integrated circuit interconnections; network routing; system-on-chip; gigascale ASIC design; gigascale SoC design; soft intellectual property cores; system-level simulation; system-on-chip; wave-pipelined multiplexed interconnect routing; Application specific integrated circuits; Routing;
Conference_Titel :
SOC Conference, 2005. Proceedings. IEEE International
Conference_Location :
Herndon, VA
Print_ISBN :
0-7803-9264-7
DOI :
10.1109/SOCC.2005.1554481
