DocumentCode
2722674
Title
A New Breed of Power-Aware Hybrid Shifters
Author
Ramadoss, Raghavan
Author_Institution
Pennsylvania State Univ., University Park, PA
fYear
2005
fDate
19-23 Sept. 2005
Firstpage
143
Lastpage
146
Abstract
The paper proposes a smart hybrid of the barrel and logarithmic shifter, to address the hardware complexity issue of the former, and the speed issue of the latter. Transistor level layout of the 16, 32 & 64-bit versions of each shifter was laid out using the state-of-art 70nm processing technology. Simulation results indicate that the proposed shifter easily outsmarts its counterparts in terms of power, delay and area complexities
Keywords
circuit complexity; integrated circuit layout; logic design; low-power electronics; microprocessor chips; 70 nm; barrel shifter; logarithmic shifter; power-aware hybrid shifters; transistor level layout; Computational modeling; Computer architecture; Context awareness; Decoding; Delay; Design optimization; Embedded computing; Hardware; Switches; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2005. Proceedings. IEEE International
Conference_Location
Herndon, VA
Print_ISBN
0-7803-9264-7
Type
conf
DOI
10.1109/SOCC.2005.1554482
Filename
1554482
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