ASSIST (Allied Signal´s Standardized Integrated Scan Test)

A system-level testability approach has been developed for testing VHSIC (very-high-speed-integrated-circuit) level ASICs (application-specific integrated circuits), memories, and board/system-level interconnections. A structured approach to testability, which is implemented with a minimum impact on current design practices, is discussed. A fixed instruction set is defined so that a single testability controller, a single testability module, and scan based cells can be developed to meet all testability requirements. The testability approach has many features, including visibility functions for normal and test data, for enhanced observability. The isolation of failures on boards or devices can be accomplished with the debug facilities. Device and memory initialization is executed through the testability bus. At-speed testing can be implemented to detect the process defects which cause timing-related faults