DG-SRAM: a low leakage memory circuit

The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. This gate leakage current coupled with the subthreshold leakage, results in a dramatic increase in total leakage power. Hence, efficient power reduction strategies that directly address the gate leakage component are necessary. In this paper, we present a diode-gated SRAM (DG-SRAM) that uses two additional NMOS (or PMOS) transistors to decrease the gate leakage in very deep sub-micron (VDSM) cache and embedded memories. Our simulation results on 65nm process (Berkeley Predictive Technology Model) for an oxide thickness of 1.5nm indicate a reduction of about 69% of the gate leakage and 65% of total leakage for NMOS-connected DG-SRAM as compared to the conventional SRAM, with minimal area overhead and no significant loss in performance or stability.