Measurement of die stresses in microprocessor packaging due to thermal and power cycling

The increasingly complex packaging used in modern workstations and servers transmits a complicated set of mechanical loads to the microprocessor. Increasing die size, high CTE ceramic substrates, lead free solder joints, and ever increasing power requirements have led to increased die stress levels in packaged microprocessor die. Such stresses can degrade silicon device performance, as well as damage the copper/low-k interconnect layers, and in extreme cases, mechanical failure of the die may occur. In previous work of the authors, on-chip piezoresistive stress sensors have been utilized to quantify stress levels induced by microprocessor packaging processes such as flip chip solder joint reflow, underfill cure, and lid attachment. Good correlation has been obtained between the test chip measurements and finite element simulations of the flip chip ceramic ball grid array (FC-CBGA) component assembly process. In the current work, we have extended our past studies on the FC-CBGA microprocessor packaging configuration to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After vari- us durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental test chip stress measurements were correlated with finite element simulations of power and thermal cycling events. A sequential modeling approach has been utilized to predict the build-up of die stress. The utilized method incorporates precise thermal histories of the package, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, good correlation has been obtained with the sensor data measured during thermal and power cycling.