Title :
Wafer-Level Compliant Bump for 3D Chip-Stacking
Author :
Watanabe, Naoya ; Kojima, Takeaki ; Asano, Tanemasa
Author_Institution :
Center for Microelectron. Syst., Kyushu Inst. of Technol., Fukuoka
Abstract :
We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device
Keywords :
MOSFET; integrated circuit interconnections; solders; wafer bonding; 3D chip-stacking; bump bonding; interchip connection; wafer-level compliant bump; Capacitive sensors; Closed loop systems; Gold; Lithography; MOSFET circuits; Resists; Strain measurement; Temperature; Testing; Wafer bonding;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0181-4
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2006.251100
