• DocumentCode
    2722878
  • Title

    Wafer-Level Compliant Bump for 3D Chip-Stacking

  • Author

    Watanabe, Naoya ; Kojima, Takeaki ; Asano, Tanemasa

  • Author_Institution
    Center for Microelectron. Syst., Kyushu Inst. of Technol., Fukuoka
  • fYear
    2006
  • fDate
    24-26 April 2006
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device
  • Keywords
    MOSFET; integrated circuit interconnections; solders; wafer bonding; 3D chip-stacking; bump bonding; interchip connection; wafer-level compliant bump; Capacitive sensors; Closed loop systems; Gold; Lithography; MOSFET circuits; Resists; Strain measurement; Temperature; Testing; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems, and Applications, 2006 International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    1524-766X
  • Print_ISBN
    1-4244-0181-4
  • Electronic_ISBN
    1524-766X
  • Type

    conf

  • DOI
    10.1109/VTSA.2006.251100
  • Filename
    4016636
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2722878