DocumentCode
2722909
Title
Microstructure and stress characterization around TSV using in-situ PIT-in-SEM
Author
Gyujei Lee ; Min-jae Choi ; Suk-woo Jeon ; Kwang-Yoo Byun ; Dongil Kwon
Author_Institution
PKG R&D, Hynix Semicond. Inc., Icheon, South Korea
fYear
2012
fDate
May 29 2012-June 1 2012
Firstpage
781
Lastpage
786
Abstract
Many studies have characterized the residual stress around TSV by using direct experimental measurement, finite element simulation, and microstructural analysis. The experimental approach is very useful in its speed and direct compatibility with processing, but cannot be used under all circumstances. Instrumented indentation testing, on the other hand, has many advantages: easy sample preparation and simple algorithms lead to a simple characterization of the micropartial stress between samples with the load difference at the same indentation depth. However, the current indentation method has the weak point that we cannot measure the residual stress when the stress-free state does not exist. Here we suggest a new algorithm to measure residual stress without knowledge of the stress-free state by analyzing the plastic pile-up mechanism around the contact area due to residual stress and using the invariant indentation properties obtained from the stressed state. We introduced this new algorithm into TSV-stress analysis to obtain the KOZ (keep out zone). In addition, we used in-situ SEM (scanning electron microscope) indentation to characterize more accurately the KOZ in the silicon around TSV, even in very minute areas.
Keywords
crystal microstructure; finite element analysis; indentation; integrated circuit measurement; integrated circuit testing; internal stresses; scanning electron microscopy; stress analysis; three-dimensional integrated circuits; KOZ; TSV-stress analysis; contact area; current indentation method; direct experimental measurement; finite element simulation; in-situ PIT-in-SEM; indentation depth; instrumented indentation testing; invariant indentation properties; keep out zone; micropartial stress characterization; microstructural analysis; microstructure characterization; plastic pile-up mechanism; residual stress; scanning electron microscope; stress-free state; Residual stresses; Scanning electron microscopy; Silicon; Stress measurement; Testing; Through-silicon vias; KOZ (keep out zone); PIT (picoinstrumented indentation testing); TSV (through silicon via); in-situ SEM indentation; micropartial residual stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4673-1966-9
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2012.6248921
Filename
6248921
Link To Document