A novel scallop free TSV etching method in magnetic neutral loop discharge plasma

Author

Morikawa, Yasuhiro ; Murayama, Takahide ; Sakuishi, Toshiyuki ; Yoshii, Manabu ; Suu, Koukou

Author_Institution

Inst. of Semicond. & Electron. Technol, ULVAC Inc., Shizuoka, Japan

fYear

2012

fDate

May 29 2012-June 1 2012

Firstpage

794

Lastpage

795

Abstract

In recent years, "2.5D silicon interposers" and "Full 3D stacked" technology for high-performance LSI has attracted much attention since this technology can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked LSI. 2.5D and 3D Si integration has great advantages over conventional two-dimensional devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing.

Keywords

etching; integrated circuit interconnections; integrated circuit packaging; large scale integration; low-power electronics; parallel processing; plasma materials processing; three-dimensional integrated circuits; 2.5D silicon interposers; full 3D stacked technology; high performance LSI; interconnection problems; low power consumption; magnetic neutral loop discharge plasma; packaging density; parallel processing; scallop free TSV etching; through silicon via; wire length; Etching; Fabrication; Iterative closest point algorithm; Plasma density; Silicon; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

978-1-4673-1966-9

Electronic_ISBN

0569-5503

Type

conf

DOI

10.1109/ECTC.2012.6248923

Filename

6248923