DocumentCode
2722948
Title
Coupling Advanced Atomistic Process and Device Modeling for Optimizing Future CMOS Devices
Author
Colombeau, B. ; Yeong, S.H. ; Pandey, S.M. ; Benistant, F. ; Jaraiz, M. ; Chu, S.
Author_Institution
Chartered Semicond. Manuf. Ltd, Singapore
fYear
2006
fDate
24-26 April 2006
Firstpage
1
Lastpage
2
Abstract
For the first time, we show the coupling between advanced atomistic process and device modeling and its applicability for 65nm PMOS and NMOS technology. This technique can be used to simulate and get some important insights to improve and optimize future CMOS devices
Keywords
MIS devices; MOSFET; semiconductor device models; semiconductor process modelling; 65 nm; CMOS devices optimization; NMOS technology; PMOS technology; atomistic process coupling; device modeling; Amorphous materials; Annealing; Boron; CMOS process; Calibration; MOS devices; Medical simulation; Predictive models; Semiconductor device modeling; Semiconductor process modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2006 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
1-4244-0181-4
Electronic_ISBN
1524-766X
Type
conf
DOI
10.1109/VTSA.2006.251105
Filename
4016641
Link To Document