DocumentCode
2722957
Title
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs
Author
Nguyen, Thi ; Shi, Kaijian
Author_Institution
Synopsys Inc., Dallas, TX
fYear
2005
fDate
19-23 Sept. 2005
Firstpage
225
Lastpage
228
Abstract
A virtual hierarchical design optimization method has been developed to combine strength of the flat and the hierarchical optimization methods for efficient and quality optimization of multi-million gate designs in a distributed computing environment. A design representation "virtual hierarchy" is proposed for subdesign optimization in a distributed computing environment. The principle and the implementation details of the method are described
Keywords
circuit CAD; circuit optimisation; distributed processing; hierarchical systems; integrated circuit design; distributed computing; distributed optimization; multimillion gate designs; quality optimization; subdesign optimization; virtual hierarchical design representations; Concurrent computing; Constraint optimization; Design methodology; Design optimization; Distributed computing; Drives; Logic design; Optimization methods; Shape; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2005. Proceedings. IEEE International
Conference_Location
Herndon, VA
Print_ISBN
0-7803-9264-7
Type
conf
DOI
10.1109/SOCC.2005.1554499
Filename
1554499
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