Electrical and morphological assessment of via middle and backside process technology for 3D integration

Author

Colonna, Jean-Philippe ; Coudrain, Perceval ; Garnier, Gennie ; Chausse, Pascal ; Segaud, Roselyne ; Aumont, Christophe ; Jouve, Amandine ; Hotellier, Nicolas ; Frank, Thomas ; Brunet-Manquat, Catherine ; Cheramy, Séverine ; Sillon, Nicolas

Author_Institution

LETI, CEA, Grenoble, France

fYear

2012

fDate

May 29 2012-June 1 2012

Firstpage

796

Lastpage

802

Abstract

This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance point of view.

Keywords

CMOS integrated circuits; assembling; ball grid arrays; integrated circuit packaging; three-dimensional integrated circuits; 3D circuit; 3D integration; BGA; CMOS node; analog functions; backside process technology; bottom die; digital functions; electrical assessment; face-to-face integration assembly; morphological assessment; size 65 nm; via middle process technology; Assembly; Bonding; CMOS integrated circuits; Nails; Resistance; Silicon; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

978-1-4673-1966-9

Electronic_ISBN

0569-5503

Type

conf

DOI

10.1109/ECTC.2012.6248924

Filename

6248924