ATPG issues for board designs implementing boundary scan

The emergence of the IEEE 1149.1. boundary-scan standard facilitates structured approaches to board partitioning, allowing test generation and execution on localized logic clusters. The authors discuss a study conducted on 1149.1 board designs to examine issues associated with board-level automatic test pattern generation; (ATPG) and interfaces to a scan-based tester environment. The authors examined issues associated with ATPG at the board level, resulting impacts on the design environment, and linking the capability to a boundary-scan-based diagnostic environment. Experiment motivation, objectives, approaches results, and observations are discussed. It is concluded that efficient use of boundary-scan devices to partition logic clusters and isolate complex devices assists in reducing the circuit test generation problem to a task that can be executed by a state-of-the-art ATPG tool