Title :
A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18 μm CMOS Technology
Author :
Ching-Te Chiu ; Jen-Ming Wu ; Shuo-Hung Hsu ; Min-Sheng Kao ; Chih-Hsien Jen ; Yarsun Hsu
Author_Institution :
Department of Electrical Engineering & Institute of Communications engineering, National Tsing Hua University, Hsinchu, 300, Taiwan. E-mail: ctchiu@cs.nthu.edu.tw
Abstract :
A low power, area-efficient 10 Gb/s wide-band current-mode logic (CML) I/O interface for high-speed interconnect is presented in this paper. This interface consists of input equalizer, limiting amplifier, CML buffer and output voltage-peaking circuit. Several wide-band techniques for this work are adopted to broaden the bandwidth and realize the circuit in 10Gb/s operation. The techniques include PMOS active load inductive-peaking, active feedback and Cherry-Hooper topology. These techniques can reduce 80% of the circuit area compared to the circuit area with on-chip inductors. The integration of the input equalizer and output voltage-peaking is also verified in this paper to provide robust I/O interface for high-speed interconnect and compensate transmission signal attenuation in the backplane. This work has been implemented in a 0.18μm CMOS technology. The total power consumption of the I/O interface is only 70mW. The area of input and output interface are 0.02mm2and 0.008mm2. The input interface can operate at 10Gb/s with 40dB input dynamic range and 4mV input sensitivity.
Keywords :
Bandwidth; Broadband amplifiers; CMOS logic circuits; CMOS technology; Circuit topology; Equalizers; Feedback; Integrated circuit interconnections; Voltage; Wideband;
Conference_Titel :
SOC Conference, 2005. Proceedings. IEEE International
Conference_Location :
Herndon, VA
Print_ISBN :
0-7803-9264-7
DOI :
10.1109/SOCC.2005.1554506